1. Shodhganga@INFLIBNET
  2. Jadavpur University
  3. Department of Electronics and Tele-Communication Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/352381
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DC FieldValueLanguage
dc.coverage.spatial
dc.date.accessioned2021-12-22T09:34:41Z-
dc.date.available2021-12-22T09:34:41Z-
dc.identifier.urihttp://hdl.handle.net/10603/352381-
dc.description.abstractnewline
dc.format.extent159 p.
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleParallel architecture for logic programming
dc.title.alternative
dc.creator.researcherBhattacharya, Alakananda
dc.subject.keywordLogic Programming
dc.subject.keywordParallel Architecture
dc.subject.keywordSIMD
dc.description.note
dc.contributor.guideKonar, Amit and Mandal, Ajit K.
dc.publisher.placeKolkata
dc.publisher.universityJadavpur University
dc.publisher.institutionDepartment of Electronics and Tele-Communication Engineering
dc.date.registered
dc.date.completed2002
dc.date.awarded
dc.format.dimensions
dc.format.accompanyingmaterialNone
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Electronics and Tele-Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title page.pdfAttached File24.17 kBAdobe PDFView/Open
02_certificate.pdf33 kBAdobe PDFView/Open
03_list of publication.pdf44.95 kBAdobe PDFView/Open
04_preface.pdf298.11 kBAdobe PDFView/Open
05_contents.pdf91.82 kBAdobe PDFView/Open
06_chapter 1.pdf2.82 MBAdobe PDFView/Open
07_chapter 2.pdf1.07 MBAdobe PDFView/Open
08_chapter 3.pdf2.29 MBAdobe PDFView/Open
09_chapter 4.pdf1.04 MBAdobe PDFView/Open
10_chapter 5.pdf233.57 kBAdobe PDFView/Open
11_appendix.pdf261.04 kBAdobe PDFView/Open
80_recommendation.pdf24.17 kBAdobe PDFView/Open
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