1. Shodhganga@INFLIBNET
  2. Vellore Institute of Technology, Vellore
  3. School of Electronic Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/350254
Title: A CMOS implementation of All Digital Phase locked loop
Researcher: Vikas Balikai
Guide(s): Harish Kittur
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: VIT University
Completed Date: 2021
Abstract: newline
Pagination: 1-175
URI: http://hdl.handle.net/10603/350254
Appears in Departments:School of Electronic Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File53.14 kBAdobe PDFView/Open
02_ declaration,certificate.pdf120.14 kBAdobe PDFView/Open
03_abstract.pdf72.5 kBAdobe PDFView/Open
04_acknowledgements.pdf87.52 kBAdobe PDFView/Open
05_table of contents.pdf86.58 kBAdobe PDFView/Open
06_list of figures.pdf126.82 kBAdobe PDFView/Open
07_list of tables.pdf95.44 kBAdobe PDFView/Open
08_list of terms and abbreviations.pdf72.55 kBAdobe PDFView/Open
09_chapter 1.pdf195.12 kBAdobe PDFView/Open
10_chapter 2.pdf365.89 kBAdobe PDFView/Open
11_chapter 3.pdf340.42 kBAdobe PDFView/Open
12_chapter 4.pdf739.09 kBAdobe PDFView/Open
13_chapter 5.pdf835.01 kBAdobe PDFView/Open
14_chapter 6.pdf1.21 MBAdobe PDFView/Open
15_chapter 7.pdf114.26 kBAdobe PDFView/Open
16_references.pdf219.89 kBAdobe PDFView/Open
17_list of publications.pdf96 kBAdobe PDFView/Open
80_recommendation.pdf1.37 MBAdobe PDFView/Open
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