Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/347821
Title: Numerical Simulations and Analysis of Heterojunction Tunnel Field Effect Transistor for Low Power and HighSpeed Applications
Researcher: Minaxi Dassi
Guide(s): Sharma, Rajnish and Madan, Jaya
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Chitkara University, Punjab
Completed Date: 2021
Abstract: Tunnel Field Effect Transistors (TFETs) have proved themselves as a better choice for the replacement of MOSFETs due to provision of scalability and possibility of better realization of goal to achieve subthreshold swing (SS) less than 60mV/decade. However, certain constraints are required to be resolved so as to improve the performance of TFET in terms of higher ON current (ION) and lower threshold voltage (Vth). In this thesis, performance of TFET has been studied and efforts have been made to overcome these major challenges. newlineTo achieve the set of objectives, source material engineering (SME) scheme has been implemented to form a staggered type II heterojunction at the source channel junction by replacing the source material of a conventional TFET by a relatively low band gap material. That way, magnesium silicide/silicon (Mg2Si/Si) heterojunction is formed at the source channel interface of a double gate (DG) TFET. MSH-DG-TFET is proposed and all the simulation results obtained for the proposed device are compared with conventional silicon source DG-TFET (SS-DG-TFET). Silvaco Atlas TCAD simulator has been used to perform all the simulations. To authenticate the work done, all the models implemented during simulation, especially nonlocal band to band tunneling model (i.e., most important model for TFET) is calibrated with already reported experimental work. It is analyzed that the proposed MSH-DG-TFET displayed superior performance by achieving higher ION, reduced Vth and steeper SS as compared to SS-DG-TFET. MSH-DG-TFET obtained ION of 2.5 x 10-4 A/and#956;m, Vth of 0.26 V and SS of 10.05 mV/decade while SS-DG-TFET obtained ION of 1.5 x 10-6 A/and#956;m, Vth of 1.15 V and SS of 19.85 mV/decade. Thus, the performance parameters especially lower Vth and reduced SS achieved by the proposed device MSH-DG-TFET makes it eligible for low power and high performance analog applications. newline
Pagination: 
URI: http://hdl.handle.net/10603/347821
Appears in Departments:Faculty of Electronics

Files in This Item:
File Description SizeFormat 
80_recommendation.pdfAttached File115.51 kBAdobe PDFView/Open
certificate.pdf129.6 kBAdobe PDFView/Open
chapter _1.pdf1.01 MBAdobe PDFView/Open
chapter_2.pdf1.56 MBAdobe PDFView/Open
chapter_3.pdf828.64 kBAdobe PDFView/Open
chapter_4.pdf3.19 MBAdobe PDFView/Open
chapter_5.pdf1.13 MBAdobe PDFView/Open
chapter_6.pdf1.3 MBAdobe PDFView/Open
chapter_7.pdf108.65 kBAdobe PDFView/Open
preliminary pages .pdf266.7 kBAdobe PDFView/Open
title.pdf13.51 kBAdobe PDFView/Open
Show full item record


Items in Shodhganga are licensed under Creative Commons Licence Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0).

Altmetric Badge: