Design and implementation of efficient adder and multiplier architectures for accurate and approximate computations

Abstract

newline With the advancement of Internet of Things (IOT), portable and handheld devices, there are some difficulties in the design of high energy efficient Very Large Scale Integration (VLSI) digital circuits. Some of the real time applications like image classifications, face recognition, DSP applications, automatic driverless car, neural network, Fuzzy system etc., do not require accurate computation. So approximation is preferred in arithmetic circuits and systems to attain low power consumption with less accuracy. In signal processing applications, energy consumption is mainly due to arithmetic operations like addition, subtraction, multiplication and division. So, it is necessary to design a power efficient adder and multiplier. This research work is focuses on the design of accurate adder, approximate adder, accurate multiplier and approximate multiplier with an application to design an area efficient and power efficient convolution layer architecture. newlineModified Flagged Binary adder (MFBA) is proposed as an accurate adder that performs four different operations (A+B, A+B+1, -(A+B+1), -(A+B+2)) in a single architecture which eventually leads to low area. Based on the control signals, the mode of operation is selected. It consists of modified preprocessing stage, modified prefix tree, modified flagged inversion cell. The generate (G), propagate (P) and intermediate signal (R) are computed in the preprocessing stage. In modified prefix tree, instead of individual bits, the pair of bits (A1A0, B1B0) is used for execution. Single carry is computed for the pair of bits and it is used to stimulate the next pair of inputs. So, there is simultaneous execution of multiple blocks which leads to the parallel operation. newline newline