FPGA implementation of optimized DDC and DUC for software defined radios

Abstract

In order to overcome the existing gaps and tradeoffs related to FPGA based DDC and DUC implementation, the main objective of this research work is to design an efficient DDC and DUC on low cost multiplier based FPGA target device to provide optimized Speed, resource utilization and consumption. In this research work different DDC and DUC sections e.g. DDS, pulse shaping filter decimators and interpolators have been individually optimized and then cascaded together to develop optimized VHDL code and RTL logic. Finally RTL logic has been efficiently floor planned to achieve optimized placement and routing of the developed DDC and DUC designs on Virtex II Pro based xc2vp30 target FPGA. The results show optimized speed performance, resource utilization and consumption of developed designs as compared to existing ones to provide effective solution for SDR applications. newline