Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/345643
Title: Design of body channel communication for wireless applications
Researcher: Vijayalakshmi, S
Guide(s): Nagarajan, V
Keywords: Engineering and Technology
Engineering
Engineering Electrical and Electronic
Body channel communication
Data communication
University: Anna University
Completed Date: 2019
Abstract: newline The present-day world is becoming near to totally automated one as we can observe many technological changes are happening every day. It is necessary to study and enlarge the wireless communication to meet the challenges of rowing application needs. With reference to other types of wireless data transmission, Body Channel Communication (BCC) is considered to be the best one due to its reliability, energy efficiency and stability. The human body skin is considered as the medium for transmission in BCC. The BCC is not affected by human body motion. Thereby the human body is used with the wideband BCC signals. The transceiver consists of a transmitter through which the encoded data is sent. The encoded data is further sent through the human body channel. The receiver receives the signal. The signal is amplified by an AFE-PCB. However, in the channel communication of the human body, some interference is occurred by the effects of body antenna. The main purpose of this research is to reduce Bit Error Rate (BER), which appears in the long-range wireless communications, wherein the human body is made as to the effective communication channel. The error-free communications and data handling applications are making use of the Error Correcting Codes (ECCs). The main aim of the research is to measure the BCC-Time domain characteristics which are used with different types of ECCs at different signal frequencies and at transmission distances. For the purpose of using different transceiver design architectures and ECC programs, the state of the art Field Programmable Gate array (FPGA) is used. The FPGA is used for the purpose of reducing power consumption, for increasing the data reliability, to increase the data speed rate and to reduce the chip size. newline newline
Pagination: xxiv,162 p.
URI: http://hdl.handle.net/10603/345643
Appears in Departments:Faculty of Electrical Engineering

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02_certificates.pdf94.4 kBAdobe PDFView/Open
03_vivaproceedings.pdf234.11 kBAdobe PDFView/Open
04_bonafidecertificate.pdf140.71 kBAdobe PDFView/Open
05_abstracts.pdf132 kBAdobe PDFView/Open
06_acknowledgements.pdf18.36 kBAdobe PDFView/Open
07_contents.pdf19.23 kBAdobe PDFView/Open
08_listoftables.pdf11.59 kBAdobe PDFView/Open
09_listoffigures.pdf350.27 kBAdobe PDFView/Open
10_listofabbreviations.pdf24.24 kBAdobe PDFView/Open
11_chapter1.pdf555.92 kBAdobe PDFView/Open
12_chapter2.pdf169.53 kBAdobe PDFView/Open
13_chapter3.pdf826.59 kBAdobe PDFView/Open
14_chapter4.pdf987.72 kBAdobe PDFView/Open
15_chapter5.pdf1.15 MBAdobe PDFView/Open
16_chapter6.pdf879.47 kBAdobe PDFView/Open
17_chapter7.pdf1.09 MBAdobe PDFView/Open
18_conclusion.pdf137.72 kBAdobe PDFView/Open
19_references.pdf397.52 kBAdobe PDFView/Open
20_listofpublications.pdf134.24 kBAdobe PDFView/Open
80_recommendation.pdf67.21 kBAdobe PDFView/Open
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