Improving intrusion detection system with efficient memory optimization in internet of things applications

Abstract

Intrusion detection is an approach to security that also emerges in the networked environments. Formerly, Intrusion detection began as a technique for detecting masqueraders and misfeasors in standalone systems, but in the few years the focus of intrusion detection has moved to towards networks. Wireless-oriented Intrusion Detection Systems (WIDSs) is a source of events for the analysis on distributed system composed of many hosts and network links. WID Systems are also capable of comparing signatures for similar packets to link and drop harmful detected packets which have a signature matching the records in the WIDS. The goal of WIDS is to detect attacks that involve the network and may span different hosts. For maximum effectiveness, WIDSs should be able to interoperate with hostbased IDSs so that misuse patterns include both network events and operating system events. So, the main function of an intrusion detection system is to perform string pattern matching. Memory architecture is a main part of hardware approaches. Through the memory architecture memory pattern is reduced and fast matching is achieved in Network Intrusion Detection System. In this memory architecture, the string patterns are taken as input which is compiled by finite state machine. As a result substrings that match to string patterns are detected. In order to achieve high security as of the networking domain are considered in current scenarios, various methods have been proposed based on the software for pattern matching. But approaches based on software do not provide adequate scalability and reconfigurability to today s level of security provisioning. In order to give enough security in Wireless Intrusion Detection System, this project work moves towards the hardware-based approaches. It provides a high level of security. Hardware based approaches mainly concentrate on memory efficiency in pattern matching. The second phase of this work provides a novel proposed technique, a new algorithm which offers an effectual memory for pattern matc