1. Shodhganga@INFLIBNET
  2. Vellore Institute of Technology, Vellore
  3. School of Electronic Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/344641
Title: Design and Analysis of Low Power Content Addressable Memory Circuits and Architectures with Different Logics and Technologies
Researcher: S V V Satyanarayana
Guide(s): Sriadibhatla Sridevi
Keywords: 
Low Power Content Addressable Memory
University: VIT University
Completed Date: 2020
Abstract: newline
Pagination: 1-124
URI: http://hdl.handle.net/10603/344641
Appears in Departments:School of Electronic Engineering

Files in This Item:
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01_title.pdfAttached File50.09 kBAdobe PDFView/Open
02_ declaration,certificate.pdf32.82 kBAdobe PDFView/Open
03_abstract.pdf23.81 kBAdobe PDFView/Open
04_acknowledgement.pdf25.5 kBAdobe PDFView/Open
05_table of contents.pdf23.48 kBAdobe PDFView/Open
06_list of figures.pdf27.75 kBAdobe PDFView/Open
07_list of tables.pdf20.08 kBAdobe PDFView/Open
08_list of terms and abbreviations.pdf23.92 kBAdobe PDFView/Open
09_chapter 1.pdf50.83 kBAdobe PDFView/Open
10_chapter 2.pdf313.15 kBAdobe PDFView/Open
11_chapter 3.pdf338.42 kBAdobe PDFView/Open
12_chapter 4.pdf341.11 kBAdobe PDFView/Open
13_chapter 5.pdf465.54 kBAdobe PDFView/Open
14_chapter 6.pdf548.82 kBAdobe PDFView/Open
15_chapter 7.pdf1.03 MBAdobe PDFView/Open
16_chapter 8.pdf26.63 kBAdobe PDFView/Open
17_references.pdf44.94 kBAdobe PDFView/Open
18_list of publications.pdf27.31 kBAdobe PDFView/Open
80_recommendation.pdf1.11 MBAdobe PDFView/Open
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