FPGA implementation of high speed and low power viterbi decoder using reverse algorithm of convolution encoder

Abstract

Present day advancement in communication system needs reliable and efficient transmission of information over varying communication channels. Error detection and correction is a major concern and plays a vital role in meaningful data recovery. Forward error correction (FEC) system, Convolutional coding is used restrictively in communication systems and yields reasonably a good result. However, the majority of existing fixed length source encoders used in transmission over noisy channels adopt grouping of data, and the chances are that source encoder may contain some excess left over. The aim of the research is to design a low power and high-speed VLSI design for a Viterbi decoder for limiting the calculation complexity and power utilization. It empowers to distinguish the issue of wastage of power utilization in the Viterbi decoder. This exploration looks at the changed low power structures of the Viterbi decoder and their executions. Four unique systems of low power design approaches are depicted and connected to outline the decoder keeping in mind the end goal to enhance its power productivity. The proposed plans are confirmed by simulations on both programming and equipment. newline