High Performance VLSI Architectures for Discrete Transformations

Abstract

The real world applications of digital signal/image processing demand high performance VLSI circuits. This work uses an incremental design approach to achieve higher performance. The first part of this work optimizes the basic building blocks of digital signal processing in area, delay, and power. In the second part, these optimized building blocks are used to design the discrete transforms. The proposed basic building blocks by this work are high speed multiplexer - which is designed by the decomposed tree of smaller multiplexers with less delay, floating point multiply and accumulator (MAC) - eliminates the separate accumulator by combining the previous result as a partial product of the present multiplication, quarter precision n * n-bits multiplier/MAC - used to perform four n/2 * n/2 or two n * n/2 or one n * n-bits multiplication(s)/MAC(s) in parallel. In case of high performance discrete transformations, fast Fourier transform (FFT), discrete wavelet transform (DWT), and discrete orthogonal multi-transform on chip (DOMoC) are considered. The quarter precision multiplier/MAC is used to design the convolution based 1D/2D DWT. The proposed techniques used in the lifting based 1D/2D-DWT architectures are to perform the whole operation with single proposed processing element (PE) and multiple proposed PEs. The former case optimizes the hardware cost and later case optimizes the delay. The proposed floating point fused multiply-add is used to design the proposed PE for lifting based 1D/2D DWT. The proposed technique in 1D-FFT is to bring down the number of cycles and number of Butterfly units in the existing folded and parallel architecture respectively. The proposed N-point discrete orthogonal multi-transform on chip (DOMoC) is to perform multiple forward/reverse N, N/2, N/4, ...2-point discrete orthogonal transforms like FFT, sine, cosine, Haar, Hartly, Slant, Walsh, and Hadamard transforms. The proposed designs are newlinemodeled in Verilog HDL and synthesized using 45 nm TSMC library.