Certain investigations on power and timing error minimization by incorporating flipflops in pid controller

Abstract

Timing errors are a real concern in VLSI integrated circuits when technology scales down. PVT (Process, Voltage and Temperature) variations, Resistive IR drops, transistor aging mechanisms and cross talk affect the circuit performance and increase the overall impact of timing error. This research focuses on providing design and analysis o several approaches that increase the energy efficiency, reduction of the power, Power Delay Product (PDP) and timing error in CMOS Nanometertechnologies. In VLSI integrated circuit, performance depends upon the appropriate choice of flip-flops and clock network design. Flip flop topologies are greatly effective in the growth of VLSI integrated in built circuits. These circuits have great influence on the speed of the system. At the same time, it is essential to choose the correct flip flop for a given application. The flip flop topologies are mainly used to avail high performance to achieve the desired design and also for the consumption of low power.In this research, several flip-flop topologies are analyzed and Razor Clock Gating Flip-Flop (RCGFF) using pulse triggering technique is proposed. PID controller is widely used in process and control industries. PID controller is most popular because of its low cost, robustness and easy to maintain in a large range of operating condition. Razor flip flops are incorporated in order to improvise the PID s performance, by detecting and correcting the timing errors on critical path. The proposed RCGFF improves the robustness and reduces the timing error Hence, this procedure is found to be appropriate for low power and data newline