Vlsi implementation of low power inverse fast fourier transform architecture using efficient pruning algorithm

Abstract

Recent researches are encouraged to develop a new method of designing in wireless communication systems and digital signal processors in algorithmic level and structural level. Communication modules as well as processors are improving by adopting good design methods for better design quality. Recent trends are encouraging the data speed and processing of huge data through a communication channel. Power consumption is also a major threat in the design of architectural level design. Researchers are encouraging to develop an optimized design in the sense of power consumption and speed of the system. Inverse Fast Fourier Transform is a major part in communication modules and DSP processor. IFFT includes large number of arithmetic operation during their operation. For each operation it performs large number of switching operations and consumes large amount of power. Pruning algorithms encourages reducing the number of switching activity by reducing the number of operations in Inverse Fast Fourier Transform. An enhanced pruning algorithm is utilized to reduce the number of arithmetic operations in the IFFT architecture. The performance of the improved IFFT architecture is estimated to find its suitability for the low power Wireless communication system. An arithmetic operation includes addition, subtraction and multiplication. Each arithmetic operation is designed based on the number of ones and zeros in the input data pattern. Based on the set of input data number of switching operations can be reducing by introducing the enhanced pruning algorithm to the IFFT. Each operator is programmed based on the enhanced newline