Design of efficient wallace tree and vedic multiplier architectures to implement binary32 floating point divider

Abstract

Most of the Digital operations in computing systems performed by Floating-Point (FP) arithmetic. The introduction of fused multiplier and add technique enhances design metrics of floating point (FP) arithmetic operations. Various division algorithms have been developed in last 60 years by means of introducing algorithms in subtractive and multiplicative categories. The challenges faced by division and square root units are well analyzed and are addressed the design challenges of Multiplicative algorithms such as Newton Raphson. Usually NR based dividers are very fast due to its quadratic convergence. For high speed designs, Newton Raphson (NR) based division algorithm is optimal choice to SRT division algorithms. For NR division, NR calculations and choosing right initial values are important for better precision and accuracy. The NR computational calculations are performed by iteratively using 32-bit FP multiplier and adder. In our work, we proposed new method to approximate initial values of 1/b, to overcome the problems faced by Goldschmidt (incorrect rounding) and Markstein (poor precision). This research work proposes 32-bit FP division using Newton-Raphson technique using Wallace Tree multiplier and Urdhva Tiryakbhyam multipliers with pipelining method. The proposed dividers could be used as an IP core and an optimal choice to speed up FP operations in DSP and SoC applications. It improves rounding accuracy with reduction in area overhead. The operands are represented in IEEE 754 standard. The operation and results are validated through simulation using VIVADO software and implemented on Xilinx-7 series, ARTIX field programmable gate array. newline