Investigation of meta heuristic algorithms based cascade control strategy for current harmonics suppression using interleaved DC DC sepic converter

Abstract

Recent technological developments in personal computers, mobile phones, robotics, space craft applications etc., involve the use of fast generation microprocessors. Switched Mode Power Supplies (SMPS) are used for powering the processors used in the aforesaid devices. The design of SMPS plays a vital role in achieving the desired performance of the system. The input current of SMPS has high harmonic content and relatively low Power Factor (PF) due to the presence of switching devices. Power Factor Correction (PFC) suppresses the current harmonics and shapes the input current of the power supply to maximize the real power available from the mains. Suppression of current harmonics also minimizes the interference with the other devices being powered from the same source. newlineVarious methodologies for designing PFC circuit in modern SMPS have been developed over the past few years, each with its own merits and demerits. PFC circuit is essentially required in SMPS for meeting the regulatory requirements in terms of % Total Harmonic Distortion (THD), prescribed by international standards such as IEC61000-3-2, IEEE 619 etc. Suppression of input current harmonics plays a major role in improving the PF of SMPS. newline newline