Investigations on low power vlsi sram memory cells and array structures

Abstract

Very Large Scale Integration (VLSI) is the present level of computer microchip miniaturization. It is the creation of an Integrated Circuit (IC) by merging thousands of transistors into a single chip. Power dissipation has been a major issue in the design of System on Chip (SoC) using the contemporary submicron technologies. newlineTo increase the driving capability and switching speed, a transistor is being scaled down to nanoscale dimensions. For the creation of every new Complementary Metal Oxide Semiconductor (CMOS) technology, efficient rightness of design and its constraints have become further perceptive to the rising leakage components and circuit parametric deviations. These disparities in process parameters strictly change the capacity of geometry transistors used frequently in area reserved designs like Static Random Access Memory (SRAM) cells. Hence there are numerous design efforts for designing nanometer SRAM cells. Random Access Memory (RAM) is preferred mostly in situations wherein memory should perform both read and write operations. SRAM is a Static RAM cell that can store data as long as power is applied to the device. As the power dissipation of Dynamic RAM (DRAM) is high, power-optimized SRAM cell can be utilized to replace DRAM cell though the cost and size of DRAM cells are less compared to SRAM cells. There are many low power VLSI design techniques to realize low power and low voltage SRAM cells. To achieve low power dissipation, forcefully reducing supply voltage and biasing performances like source biasing and body biasing during sleep mode relics the most efficient ways newline newline