The implementation of integrated algorithm on area delay and power in vlsi circuits using approximate calculation and lutclaqtl method

Abstract

The phenomenal growth in the electronic industry is achieved through the rapid advancement in VLSI and the system design process. The implementation of low power consumption , reduced area and delay in process of technology domain is driven by decisive change process. With the invent of VLSI technologies in the computer application devices such as laptops, notebooks, PCs, mobile phones in domestic and telecommunication ,this industry is growing at a fast pace. The cutting edge of this technology is supporting low consumption of power reducing the generation of heat and thereby increasing the performance of the circuit process. The objective of the study is the implementation of the circuit process and design low electric power consumption in VLSI circuits. The most common electronic usages and drawback in the functioning and default power is due the logical design in the circuits. In VLSI arithmetic and logic calculation, precise implication are obtained by its architect circuit design. It is quite evident that several design and application does not require precise results. This study focus on an application of improved algorithm logical function with reduced power consumption and approximate values in VLSI design . These techniques are widely used in applications where power consumption is very less. In VLSI circuits, power consumption and time delay in arithmetic and logical functional is due to multiple operations like addition, multiplication and data conversion process. Effective implementation of approximate multipliers in Partial Product Reduction (PPR), is highly effective and increases the performance to greater extend than the traditional multipliers. To design low power consumption models in VLSI circuits, the implementation and design of fabrication on the chip on fast multipliers such as (CSK) carry skip adder, (CSA) Carry Select Adder (CLA) carry look ahead adder and (ETL)error tolerance adder, those multipliers always have been trade-off between power newline