Performance evaluation of full adders based on adiabatic logic cell and power gated cell

Abstract

newlineIn the contemporary electronics era of miniaturized and sophisticated equipments in harmony with the VLSI technology, there is an essential need to design energy efficient full adder which is the most important sub circuit in building the major circuits like higher order adders, multipliers, arithmetic units etc. This major circuit when embedded inside the high performance processors and in other real time application units utilized for image and video processing will have much lower power consumption. Focusing in this direction, in this research work initially, analysis of power and of the digital logic based full adder versions like 28T CMOS Based full adder, 14T pass transistor with Transmission gate full adder and 16T pass transistor with Transmission gate full adder. Then an energy efficient full adder is designed based on adiabatic logic. The digital circuits designed using adiabatic logic will have negligible amount of exchange of energy in the surrounding environment. Therefore the application circuits based on this logic will have negligible energy loss due to heat dissipation. Also because of recycling of the energy happens in this logic the overall power consumption of the circuits will be much lower when compared to the same circuits built using CMOS based logic. Hence, in the conventional Energy Efficient Adiabatic Logic (EEAL) based full adder design modifications in the device level is carried out to obtain the proposed modified EEAL based full adder cell. The proposed full adder cell reduces the power consumption by 98.49%, 90.93% and 89.37% respectively when compared to 28T CMOS Based full adder, 14T pass transistor with newline newline