Design and Implementation of Multipliers based upon Vedic Mathematics

Abstract

Multiplication operation finds enormous applications in the field of digital electronics such as in Arithmatic and Logic Units, Digital Signal Processing, image compression, cryptography, Digital Communication, graphics, embedded systems and various scientific computations. It is basically the most frequently used operation in a digital computer and also forms the basis for various complex operations. There are various multiplication techniques to design a multiplier. Depending upon the technique used there are various types of multipliers those produce accurate results, having simple and regular structure, offers low power consumption, lesser area and have high speed of operation which make them suitable for low power and high speed VLSI designs. Hence, high speed of operation, less area, low power consumption, regular structure and accuracy are important parameters for the design of multiplier in VLSI. newline newlineIn the present work, Vedic mathematics is used to design the multipliers. Vedic mathematics is based upon 16 sutras (Formulas). The study found that Urdhava Triyakbhayam sutra is most efficient sutra in terms of delay and power consumption, and is suitable for all type of numbers, either small or large. The multipliers designed by this sutra has simple and regular structure. Three multipliers design for 2x2 bit quadratic equation, 4x4 bit quadratic equation and 8x8 bit quadratic equation have been proposed. All these multipliers are coded using VHDL. These designs are effective to multiply two quadratic equations in practical scenarios, if we know the values of variables and constant of quadratic equation. A BCD multiplier for the multiplication of two BCD numbers is also presented. All these multipliers designs are implemented on Xilinx devices and various parameters such as area, power dissipation and delay has been calculated for these designs. newline newline