Design of low power all digital phase locked loop architecture using submicron cmos technology

Abstract

Phase Locked Loops (PLL) are used in almost every communication system. Some of its uses include recovering the clock from digital data signals, phase modulation, phase demodulation, recovering the carrier from satellite transmission signals and as a frequency synthesizer. PLL is generally implemented using analog components, which are called Analog PLL (APLL). APLLs have been widely used for clock generation, frequency synthesis with excellent performance and high frequency range. The primary challenges in APLL are high power consumption, large area, scalability and high phase error due to clock matching. All Digital PLLs (ADPLL) solve the problems of the APLL where the ADPLL have low power consumption, small area and scalability across different technology nodes. Fully digital PLLs have better noise immunity and better tolerance to bias drifts and Process Voltage and Temperature (PVT) variations. ADPLL uses a phase frequency detector as an alternative of a phase detector, Digitally Controlled Oscillator (DCO) instead of a Voltage Controlled Oscillator (VCO), control circuit duplicating the functionality of a loop filter and a fixed frequency detector. This design is very much appropriate for system on chip applications and can be automatically implemented with standard cell libraries. The main objective of this research is to design low power ADPLL architecture. The plan comprises four primary blocks which viz. Phase Detector (PD), Loop Filter (LF), DCO and frequency divider. The PD is considered as the core of the ADPLL as it devours the most of power for the entire framework. In this exploration work four diverse methodologies are created to enhance the execution of low power ADPLL by considering different elements of low power applications In research, the most part manages display and check of an ADPLL concerning its architecture, usefulness, phase noise demonstrating and examination. It begins with a correlation of current frequency synthesizers including direct simple digital synthesis and indirect synthesis using ADPLL. Keeping in mind the end goal to gain overall comprehension of ADPLL, a behavioral hypothesis in both time and power has been conducted in detail. Investigation demonstrates that the prohibitive modules (phase detector and loop filter) of proposed ADPLL to be located in Time to Digital Converter (TDC) and DCO. It is additionally demonstrated that the transmission capacity and settling time of ADPLL is dictated by corresponding and incorporating parameter of loop filter. The proposed circuit techniques and architecture improvements are verified, respectively with four model design. newline