Certain investigations on triple and double adjacent error detection correction and optimized computation of syndrome bits in cache memory

Abstract

The contemporary electronic devices housed with memory and are paramount requirement to execute and to meet out the very objective and purpose of the devices. Nevertheless, cache memories employed in the electronic systems are susceptible for soft errors very frequently, however soft errors are detectable and subsequently can be corrected too. Changes in the collected and stored values are known as soft errors. Thus novel techniques are required to mitigate the soft error. The failures in the stored cells can be set right by deploying the Error Correcting Codes (ECC) which is the best option and are pertinent for the applications like memory and communication etc. In this thesis certain optimization techniques are proposed to reduce the encoder and decoder computation time of cache memory that is affected by soft error and by implementing ECC such as cyclic and block codes. Error that is adjacent by a width of three and two bits are the prime concern of this thesis. Optimised Golay code (23, 12) and new block code size (32, 19) which is also optimised are presented. Nevertheless, cyclic code is efficient compared with block code however, the prime concern of the thesis is to address the triple and double adjacent errors which also includes single bit error, in this regard built-in capability of Golay code is optimised and used for comparison. Furthermore, the (32, 19) block code is proposed in which both encoder and decoder sections are optimised. In the encoder part a fast computing algorithm is proposed to encode the data with parity, and an optimised decoder is proposed to compute the syndrome bits. Moreover in the architecture of both the proposed codes parallel in parallel out shift registers are used for fast computation, consequently clock cycles required is less. In this thesis all the proposed methods are described in hardware description language Verilog and synthesised using 180 nm library of cadence tool. The results are listed and compared in which the simulation results shows significant percentage of reduction for the parameters such as area, delay and power for the cache memory built using Static Random Access Memory (SRAM). Optimised Golay code (23, 12) is efficient in comparison with other proposed and existing methods. However with 39% increase in code length of proposed (32, 19) block code compared to proposed cyclic code, the results show a very marginal increase in area, delay and power for (32, 19) which can be compensated for the increase in data bits against the proposed optimised Golay code (23, 12). Furthermore the proposed (32, 19) block code matches with the standard size of the cache memory this makes the proposed block code to be effective and efficient to mitigate the double and triple adjacent errors newline