Power aware dft techniques for scan based vlsi circuits

Abstract

Power consumption is one of the important factors to be considered in VLSI circuits and device implementations. Embedded memories occupy almost 95% of area in the System-on-Chip (SoC) applications. Memory testing is an important task and a single memory chip can be tested in normal mode, whereas, multiple memories can be tested in parallel mode. Ideally during test mode, the power consumption is doubled as that of the functional mode and test-power should be within the power threshold constraint of the chip. If test power exceeds the power constraint of the chip, there is a possibility of memory and chip damage and this leads to built-in testing instead of external memory testing. Memory Built-In Self-Test (MBIST) is one of the popular methods for testing the embedded memory in digital logic circuits. The use of MBIST for memory testing is advantageous since it allows automatic test generation with fault coverage upto 99% and also reduces the chance of race conditions in the circuit. It consists of an Address Generator (AG) to generate the memory address and a Test Pattern Generator (TPG) to generate the test pattern for testing the memory. The AG in the MBIST provides significant contribution and is responsible for its fault detection capability. Many of the existing memory testing techniques that are available nowadays focus on reducing the test power which has direct impact on evaluating the effectiveness of testing techniques. Dynamic power dissipation depends on switching activities that occur during application of test vectors in test mode. Hence, reducing the switching activity in test phase will have direct impact in reducing the power in VLSI circuits. The initial research work in this Thesis proposes the design of power efficient address generator for MBIST to reduce the switching activity. The proposed address generator reduces the bit-transition between two successive address generated in each clock cycle during test verification. The reduction in switching activity contributes to major improvement i