Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/339872
Title: Embedded evolvable hardware design of digital circuits using bio inspired algorithms
Researcher: Ranjith, C
Guide(s): Joy Vasantha Rani, S P
Keywords: Evolvable hardware
Bio-inspired algorithms
University: Anna University
Completed Date: 2019
Abstract: Evolvable Hardware (EH) deals with the evolution or design of circuits using evolutionary techniques. The circuits are evolved by dynamically configuring the circuit parameters. The evolved circuits do change their parameters adaptively, with changes in the environment. The term EH is composed of two parts: the Evolutionary Algorithm (EA) and the reconfigurable devices. The EA or bio-inspired algorithms search for circuit configurations based on certain fitness criteria, and the reconfigurable devices provide a platform for evolving the circuits by configuring the bits. Here, the main focus of research work involves digital circuits, therefore the reconfigurable devices used is Field Programmable Gate Array (FPGA) are used to evolve digital circuits. Different bio-inspired algorithms like Genetic Algorithm (GA), Memetic Algorithm (MA) and Particle Swarm Optimization (PSO) are used as the optimization algorithms to search for the configuration bits. The research focuses on the embedded EH concept, wherein the complete EH platform is embed in a single FPGA. In this method the hard or soft processor cores of the FPGA are used to run the optimization algorithm and the normal FPGA logic to evolve the circuit. This embedded mode of EH platform has the advantage of faster evolution and makes the system portable, flexible and robust in nature. The research work developed experimental models to demonstrate the embedded EH concept with intrinsic mode of fitness evaluations. The work concentrated on the evolution of simple combinational circuits, FIR filters and Adaptive Noise Cancellation (ANC) systems. The initial work gives a performance analysis of MA and GA in the evolution of combinational circuits. The complete system was built on XilinX Virtex 6 (XC6VLX240T-1FFG1156) FPGA. GA is the traditional algorithm used for the evolution of combinational circuits. The search operation through GA is slow, but also suffers from a problem known as premature convergence or getting stuck at local minima, never finding its path t
Pagination: xv,199 p.
URI: http://hdl.handle.net/10603/339872
Appears in Departments:Faculty of Information and Communication Engineering

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03_vivaproceedings.pdf94.62 kBAdobe PDFView/Open
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06_acknowledgements.pdf119.54 kBAdobe PDFView/Open
07_contents.pdf126.94 kBAdobe PDFView/Open
08_listoftables.pdf21.56 kBAdobe PDFView/Open
09_listoffigures.pdf46.9 kBAdobe PDFView/Open
10_listofabbreviations.pdf13.2 kBAdobe PDFView/Open
11_chapter1.pdf513.37 kBAdobe PDFView/Open
12_chapter2.pdf782.97 kBAdobe PDFView/Open
13_chapter3.pdf1.29 MBAdobe PDFView/Open
14_chapter4.pdf872.59 kBAdobe PDFView/Open
15_chapter5.pdf1.79 MBAdobe PDFView/Open
16_conclusion.pdf151.28 kBAdobe PDFView/Open
17_appendices.pdf393.33 kBAdobe PDFView/Open
18_references.pdf194.06 kBAdobe PDFView/Open
19_listofpublications.pdf108.75 kBAdobe PDFView/Open
80_recommendation.pdf93.03 kBAdobe PDFView/Open
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