Modeling simulation and analysis of subthreshold characteristics in dual metal dielectric engineered junctionless tunnel fet

Abstract

The perpetual downscaling of devices has achieved higher packaging density and faster switching performance. From early 1970 s, scaling the channel length has been considered as one of the most critical part in device scaling. As the physical dimensions of FET device are scaled down consistently, many undesirable Short Channel Effects (SCEs) such as Channel Length Modulation (CLM), Hot Carrier Effect (HCE), Drain Induced Barrier Lowering (DIBL), and subthreshold leakage current becomes more dominant and deteriorates the performance of the short channel devices. Scaling the channel length of the device attacks the electric flux on the drain side to penetrate into the channel region and suppressing the control of gate over the channel. Obviously, the drain side electric field will be too high to cause subthreshold leakage issues. For high-speed digital applications, the major challenge is controlling the subthreshold leakage current and to improve the device immunity against short channel effects. Also, to meet out the technological demands of the thriving semiconductor industry, researchers have accomplished several new measures to push scaling beyond the expected limits. The major driving force for the proposed research is to overcome all these above limitations with advancements in the materials science and semiconductor industry. Beginning with the search for novel devices to suppress the SCEs, Junctionless Transistors (JLT s) have evolved as the most gratifying candidate. Junctionless devices follow uniform doping. The absence of gradient doping concentration makes the fabrication process much simpler and offers low thermal budget. With regular conventional FET s, the mobility degradation and surface scattering effects become dominant and it is less encountered in junctionless devices. But, to improve the subthreshold characteristics of a device, it is always wise to choose a device that can provide subthreshold swing less than 60 mV/dec. Such a promising device to replace the shortcomings of conventional MOSFET is Tunnel FET (TFET). This is a simple gated p i n diode which turns ON by applying suitable gate bias. The underlying principle of these Tunneling FET is Band To Band Tunneling (BTBT) which allows electrons to tunnel easily from valence band of p region to conduction band of intrinsic region resulting in a current flow across the device. The OFF-state leakage current (IOFF) is also found to be minimized and hence it is more appropriate to use in low-power applications. Thus, combining the advantages of uniformly doped junctionless transistors with the tunneling effect, the proposed research work uses a unique structure called Junctionless Tunnel FET (JLTFET) which is initially a junctionless FET with uniform doping throughout the device. To convert the junctionless FET into a junctionless Tunnel FET, appropriate gate metal work functions are chosen newline