Certain investigations on design of high performance mos current mode logic certain investigations on design of high performance mos current mode logic mcml for low power and high speed applications for low power and high speed applications

Abstract

With the rapid increase in transmission speeds of communication systems, the demand for very high-speed low-power Very Large Scale Integration (VLSI) circuits is on the rise. The static Complementary Metal Oxide Semiconductor (CMOS) design style is adopted in most of the digital applications. Generally in VLSI circuits, excessive power dissipation and switching noise occurs due to leakage current which in turn affects the overall efficiency. To solve this issue, MOS Current Mode Logic (MCML) is employed in high-speed circuits. MCML in recent years have gained interest and popularity due to its high speed operation, reliable performance in comparison to the CMOS logic family. However, the major limitation of MCML is its constant static power dissipation which in turn consumes excess energy in large scale ics. To overcome this limitation, a modified MCML system is proposed to achieve characteristics such as low power dissipation, and high processing speed. In the modified MCML, the number of transistors is decreased through reduction approach and also static power dissipation is minimized by reducing the switching activity. In reduction approach, the common input of all the logic is replaced by a constant current source. This decreases the short circuit leakage current consequently reducing the switching activity and Power Delay Product (PDP). A universal gate based on the proposed system is designed and implemented in full adder and multiplier. The simulation result shows that the performance of the design is optimized in terms of power dissipation, PDP and area. With the aim of achieving further reduction in power dissipation, the Dynamic MOS Current Mode Logic is proposed. Dynamic MCML circuits integrate the benefits of modified MCML circuit and dynamic logic families. Iv In dynamic logic, charging and discharging of output generated in the modified MCML circuit is carried out by introducing cross coupled transistors. Universal gate designed based on this dynamic MCML is implemented in full adder and multiplier.