Design and implementation of high speed power efficient key dependent aes block cipher on fpga

Abstract

newline This research work presents a novel high-speed and power-efficient architecture for the FPGA implementation of Advanced Encryption Standard (AES) algorithm. Proposed design employ s a sub-pipelined architecture for each round of AES operation and modified form of Positive Polarity Reed-Muller technique (MPPRM) for SubBytes and InvSubBytes Transformation stages in all the rounds of AES operation rather than relying on Look-Up tables or CFA architectures. Advantage of avoiding large power consumption due to dynamic hazards in CFA and Look-Up table architectures is explored in this MPPRM architecture. Also all the basic building block of AES is made key-dependent rather than using the main secret key only in AddRoundKey stage. In addition, an efficient key expansion architecture which makes use of sub-pipelined and parallel operative architecture is presented in this research work. With this proposed work, an efficient AES architecture is developed, which can provide the output with a minimal delay of 30.705ns when it is implemented in Xilinx Virtex 5 Xc5vlx20t FPGA and it has shown a better avalanche effect of 58% of the times on considering 1000 pair of samples for analysis. Power consumed by this new architecture is also 22.3% improved on comparing with conventional standard AES-128. newline newline