Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters

Abstract

Three dimensional integration is one of the emerging techniques newlineto find solution for the global interconnect delay challenges faced in the newlineadvanced VLSI ULSI technology Network on Chip NOC is a novel newlinedesign paradigm in which the 3D integration can be realized for newlineincreasingly complex System on Chip SOC In a three dimensional newlineNetwork on Chip 3D NoC topology the adjacent layers are newlineinterconnected with each other by using vertical links In the fabrication newlineprocess the right candidate to realize the vertical links is Through Silicon newlineVia TSV which has several problems such as misalignment thermal newlineissues and consuming considerable chip area etc Hence the number of newlinevertical links used in a 3D NoC architecture must be minimized Design of newlinea priority based programmable arbiter is of paramount importance as its newlineperformance influences more on the operating speed of the router scheduler newlineThe objectives of this research work are to i exhibit that 3D newlineNoC minimizes chip area wire length and energy consumption compared to newlinethat of 2D NoC architecture ii evolve a vertically partially and newlineHamiltonian connected 3D NoC topology with minimum vertical links and newlineto develop a deadlock free 3D routing algorithm iii evaluate the newlineperformance of the 3D NoC topology using an analytical model and newline design a programmable prefix router arbiter and implement it in newlineFPGA for effective implementation of System on Chip SoC newline newline