Certain investigations on the design of VLSI arithmetic circuits for DSP application

Abstract

Over the past few decades, the growth of portable devices such as laptops, mobile phone and personal digital assistant has resulted in increasing demand for complex functionality with effective computation. The present day technology is known for digital systems with very high computing capabilities. The demand for high speed, low power integrated circuits for portable devices has become crucial. The never ending growing complexities of integrated circuit for future devices pose a challenging task for integrated circuit designer. Cost effective integrated circuits requires the design meeting out the challenging task to optimize power, area with high performance. Hence this research focuses on the optimization of area, power and speed of Arithmetic circuits, Very Large Scale Integrated circuits (VLSI) are widely used in Arithmetic circuits, Digital Signal Processing (DSP), Image and Video Processing applications. The performance of signal processing application depends on the effective design of the arithmetic circuit, which plays an important role in achieving performance metrics like low area, low power and high speed. The application specific or general purpose system uses addition as a basic arithmetic operation. Adders form an important part of any arithmetic unit becoming the heart of any data processing system. The performance metrics depends on the effective design of the adders in arithmetic logic and hence the design of arithmetic circuit is important in any VLSI system. The Ripple newlineCarry Adder (RCA) is designed by using buffer based full adders for overcoming the issues involved in the delay. The proposed buffer based adder is implemented in 2 bit and 3 bit Binary Common Sub expression Elimination (BCSE) constant multiplier architecture. The performance of multi bit adders varies widely in consuming power, area and speed. newline newline