Analytical modeling and simulation of gaussian doped junctionless finfets for enhanced cmos applications

Abstract

CMOS transistors have proven as one of the most promising technology in the field of micro and nano electronics. Several silicon based CMOS transistors have evolved in the last two decades. The dimension of the transistors have been incessantly reduced to increase the number of transistors in a single chip that it not only reduced the chip area but also increased the functionality and operating frequency of the chip. This nano scaled transistors are the backbone of today s quantum computing era where the smart phone, smart watches and smart technology has become an inevitable in our daily life. The most important issue confronting in VLSI technology is the power dissipation arising from the scaling of transistors. The classical MOSFETs scaling below 100 nm ensues several physical issues that degrades the performance of the chip. The issues are short channel effects such as subthreshold current, threshold voltage roll-off, Drain Induced Barrier Lowering (DIBL) and hot carrier effects. newline