Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/335200
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dc.date.accessioned2021-08-09T11:43:58Z-
dc.date.available2021-08-09T11:43:58Z-
dc.identifier.urihttp://hdl.handle.net/10603/335200-
dc.description.abstractPower leakage has been experiencing an exponential increase with the technology scaling and stretching over 30% of chip power in 90nm node and getting close to 45% in 65nm node. In this thesis, three effective techniques for reducing leakage of power in various circuits have been considered. The first one is the sleep transistor insertion technique for 4 bit CLA adder circuit. The second is the stalk technique used in footerless domino circuit. And the third is the FinFET technique used for FPGA routing architecture. Initially, in the sleep transistor technique, low-leakage PMOS transistors have been designed as header switches to switch off power supply(VDD) when the system is not in use. On the other hand, low-leakage NMOS transistors can be utilized as footer switches for controlling VSS supplies.Power gating of both the VDD and VSS is not concrete due to the low voltage headroom in sub-90nm node. The header or footer switches are often called sleep transistors which connect power supply from the stable power supply to circuit power supply or virtual power supply . There are numerous resources like these for reducing power leakage but even then an efficient power leakage system has not yet been obtained. The proposed work addresses this issue by designing a 4 bit CLA adder for leakage saving in idle mode. Based on the incoming signals, the Carry Look-Ahead Adder (CLA)clears the carry delay problem by finding the carry signals in advance. Clustering approach is used in the design of 4 bit CLA for reducing leakage.Hence, it can generate carry signals in advance from the given input values, which may enhance prediction of the next successive higher order by adding lower order bits in sequence. Then the 4-bit CLA adder is clustered using the clustering algorithm through following process. Before clustering, the proposed technique initially determines the power leakage status of all gates. newline newline newline newline
dc.format.extentxix,131p.
dc.languageEnglish
dc.relationP124-130.
dc.rightsuniversity
dc.titleEfficient leakage power reduction techniques and challenges in nanoscale cmos circuits
dc.title.alternative
dc.creator.researcherLakshmi narayanan S
dc.subject.keywordNanoscale
dc.subject.keywordCmos
dc.subject.keywordLeakage power
dc.description.note
dc.contributor.guideReeba korah
dc.publisher.placeChennai
dc.publisher.universityAnna University
dc.publisher.institutionFaculty of Information and Communication Engineering
dc.date.registered
dc.date.completed2020
dc.date.awarded2020
dc.format.dimensions21cm
dc.format.accompanyingmaterialNone
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Faculty of Information and Communication Engineering

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02_certificates.pdf256.89 kBAdobe PDFView/Open
03_vivaproceedings.pdf563.21 kBAdobe PDFView/Open
04_bonafidecertificate.pdf324.32 kBAdobe PDFView/Open
05_abstracts.pdf57.54 kBAdobe PDFView/Open
06_acknowledgements.pdf315.62 kBAdobe PDFView/Open
07_contents.pdf71.88 kBAdobe PDFView/Open
08_listoftables.pdf53.52 kBAdobe PDFView/Open
09_listoffigures.pdf71.85 kBAdobe PDFView/Open
10_listofabbreviations.pdf53.42 kBAdobe PDFView/Open
11_chapter1.pdf380.97 kBAdobe PDFView/Open
12_chapter2.pdf134.04 kBAdobe PDFView/Open
13_chapter3.pdf1.37 MBAdobe PDFView/Open
14_chapter4.pdf2.4 MBAdobe PDFView/Open
15_chapter5.pdf1.64 MBAdobe PDFView/Open
16_conclusion.pdf87.7 kBAdobe PDFView/Open
17_references.pdf123.77 kBAdobe PDFView/Open
18_listofpublications.pdf78.42 kBAdobe PDFView/Open
80_recommendation.pdf182.91 kBAdobe PDFView/Open


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