Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/335200
Title: Efficient leakage power reduction techniques and challenges in nanoscale cmos circuits
Researcher: Lakshmi narayanan S
Guide(s): Reeba korah
Keywords: Nanoscale
Cmos
Leakage power
University: Anna University
Completed Date: 2020
Abstract: Power leakage has been experiencing an exponential increase with the technology scaling and stretching over 30% of chip power in 90nm node and getting close to 45% in 65nm node. In this thesis, three effective techniques for reducing leakage of power in various circuits have been considered. The first one is the sleep transistor insertion technique for 4 bit CLA adder circuit. The second is the stalk technique used in footerless domino circuit. And the third is the FinFET technique used for FPGA routing architecture. Initially, in the sleep transistor technique, low-leakage PMOS transistors have been designed as header switches to switch off power supply(VDD) when the system is not in use. On the other hand, low-leakage NMOS transistors can be utilized as footer switches for controlling VSS supplies.Power gating of both the VDD and VSS is not concrete due to the low voltage headroom in sub-90nm node. The header or footer switches are often called sleep transistors which connect power supply from the stable power supply to circuit power supply or virtual power supply . There are numerous resources like these for reducing power leakage but even then an efficient power leakage system has not yet been obtained. The proposed work addresses this issue by designing a 4 bit CLA adder for leakage saving in idle mode. Based on the incoming signals, the Carry Look-Ahead Adder (CLA)clears the carry delay problem by finding the carry signals in advance. Clustering approach is used in the design of 4 bit CLA for reducing leakage.Hence, it can generate carry signals in advance from the given input values, which may enhance prediction of the next successive higher order by adding lower order bits in sequence. Then the 4-bit CLA adder is clustered using the clustering algorithm through following process. Before clustering, the proposed technique initially determines the power leakage status of all gates. newline newline newline newline
Pagination: xix,131p.
URI: http://hdl.handle.net/10603/335200
Appears in Departments:Faculty of Information and Communication Engineering

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11_chapter1.pdf380.97 kBAdobe PDFView/Open
12_chapter2.pdf134.04 kBAdobe PDFView/Open
13_chapter3.pdf1.37 MBAdobe PDFView/Open
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15_chapter5.pdf1.64 MBAdobe PDFView/Open
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