Some investigations on run length based test data compression techniques for efficient fault detection in application specific integrated circuits

Abstract

The test is an integral part of the integrated circuit manufacturing process and is essential to screen the defective parts before shipping the product to customers. Given the complexity of increasingly integrated circuits, there is a need for Computer-Aided Design tools (CAD) to automate the various stages of the design process. Automatic Test Pattern Generation (ATPG) is one of the most difficult problems for automating electronic design and has been a popular research topic for over thirty years. Test generation for benchmark circuits is a research problem on a large vector space proportional to the number of inputs and the number of states. Often, a fault simulation procedure is built into an automatic test pattern generation system. Delayed models used during simulation greatly affect the quality of simulation results, usually when the circuit has asynchronous parts. The delay of a logic gate and interconnection is affected by various parameters of the manufacturing process and it is difficult to model the uncertainties of the process. This research work presents algorithms for test pattern generation and stuck-at- fault defect simulation in ISCAS-89 reference circuits. Augmented Recurrence Hopping Based Run Length Coding (ARHRLC) and Reliable Low Latency Adaptive Fault Tolerant methods (RLAFT) are used for test production and fault simulation. Experimental results are presented for standard reference circuits. The proposed ARHRLC technique uses the minimal switching transition box to obtain compressed data. When applied to different standard circuits, test vector compression increases significantly using projected ARHRLC. Proposed ARHRLC solves the problem of lower compression ratio compared to previous length codes. newline