Investigations on RS decoder and viterbi decoder for forward error correction implemented on 90 nm CMOS technology

Abstract

In wired/wireless network, channel noise has a greater impact on the error has been occurred in message or data in the communication is a fundamental problem. The channel noise formulates the problem as the noise signals may oscillate around the threshold voltage level of the original signal it might be results as the bits are altered likewise such as 0 becomes as 1 and 1 becomes as 0 it arises when data or text messages are transmitted and modified the data or text messages in the receiving side this will occur the error over the initial data transmitted. To overcome above said problem, the error correction code is required for capability of correcting both burst and random error with high coding gain. Then the packet loss during the transmission process is recovered as well as energy consumption, reduced delay and data loss control over the error block. So in this research, we propose novel and#945;-factor architecture for RS decoder implemented on 90nm CMOS technology. The entire research work carries out into two different stages where each stage is interrelated. In the first stage of the research work, the main objective is to present and#945;-factor architecture of RS decoder for improving in terms of gate element, latency, coding gain and throughput. In the second stage of the research work, the main objective is to provide PLDA for efficient Viterbi decoding equalizer implement to removing the error from the received messages or data. In the first stage a research work, The Reed-Solomon decoder was developed using Verilog Hardware Description Language (HDL) and Synopsys Design Compiler (DC). The proposed architecture is developed using 90nm CMOS technology and the results are evaluated in terms of gate count, clock rate, latency and throughput. Also the calculated syndrome and KES are compared with the conventional architecture for efficiency. newline