Certain hybrid soft computing models for power estimation in CMOS VLSI circuits

Abstract

Advancement of Very Large Scale Integration (VLSI) technologies has achieved integrating millions of transistors into a single chip. This integration into a single chip results in complex circuitry and hence it is required to have minimal cost and low complex power estimation approaches. Power estimation of VLSI circuits at an initial stage is most prominent because it increases the life and stability of the circuit. It is very difficult to design and simulate a large VLSI circuit considering all probable input vectors for power measurement and estimation. Due to which power measurement is carried out using certain pair of vectors called to be and#8213;mean power consumedand#8214; vector. With the increasing utilization of convenient movable devices like mobile phones, palmtops, laptops, tablets and so on, the power consumption is a major concern that regulates the lifetime of batteries. Considering the importance of power estimation in VLSI circuits, this thesis contribution is intended to develop certain hybrid soft computing models to estimate the power accurately for the Complementary Metal Oxide Semiconductor (CMOS) circuits. The developed method does not require prior knowledge about the circuit architecture and its connections. All the proposed hybrid soft computing models employed for estimating the power in VLSI circuits should be highly scalable and reliable ones. If the power gets estimated in an accurate manner, then the feasibility in knowing other internal operations of CMOS VLSI circuit is at ease. Once the circuit power level is known, this will facilitate the designer to concentrate on other aspects like density of board, losses incurring during operational time, other related errors in the circuit and so on newline