Energy harvesting using adiabatic logic in content addressable memory for high speed applications

Abstract

newline Integrated Circuit (IC) is an inherent and integral part of any system design. The three main challenges in the design of Integrated Circuits are area utilization, power consumption and speed of operation. Tremendous transistor scaling over the past two decades paved the way for faster and denser integration resulting in the proliferation of high performance in terms of processing speed and multi-tasking at a reduced cost. This translates to an exponential increase in the system performance in terms of speed posing an enormous challenge to the power consumption of the circuits. Power consumption has become a chief concern because of the escalation in the compactness of the circuits and their speed of operation. Power dissipation affects the performance, portability and reliability of the circuit. Low power VLSI design which is an inevitable part of any IC design has attracted much attention from both the academic and industrial research communities, resulting in much peer reviewed literatures published, wherein, innovative power efficient solutions at circuit level, gate level, architectural level, and system level were reported. Recently, a lot of research is being carried out to explore the feasibility of the usage of Gallium Arsenide (GaAs), Gallium Nitride (GaN), Graphene, etc., in the design of power efficient devices. However CMOS technology remains the backbone technology for most of the IC designs. The power dissipations that usually occur in CMOS circuits are static, dynamic, short circuit and leakage power dissipation. All the existing techniques address the reduction of power dissipation. Hence there is a necessity for energy reuse to recover the energy that is wasted in the ICs. newline newline