Noise measurement and control in high performance domino logic design with improved circuit parameters

Abstract

Noise immunity is the primary concern of high-performance domino logic circuits. In general, high noise tolerance in domino logic circuits are accomplished at the cost of other circuit parameters such as speed, power degradation and area overhead. This research work has focused on the design of new domino logic styles with better noise immunity without compromising circuit parameters such as power and delay. In this work, Pseudo CMOS Keeper logic is proposed for domino circuit to achieve better noise immunity with reduced power and delay when compared with the existing noise tolerant logic circuits. The proposed logic shows Unity Noise Gain improvement of 2.7% and reduction in power delay product by 30% for a two input OR gate when compared with conventional keeper logic. The proposed logic also shows higher UNG for different operating voltages. The Pseudo CMOS Keeper logic has also attained 46% and 14% reduction in delay in comparison with the conventional keeper logic and low power dynamic keeper logic respectively. The proposed logic is also used to realize circuits such as two input OR gate, wide fan-in OR gates, two input EX-NOR gate, 4:1 multiplexer, full adder and 4x4 Vedic multiplier. The proposed Pseudo CMOS keeper logic shows better performance in terms of noise tolerance and power delay product Secondly, this research work proposes a Conditional Strong Keeper circuit to improve the noise immunity of domino logic circuits with lower power delay product compared to existing noise tolerant techniques. The conditional strong keeper employs a strong keeper to improve the noise immunity of domino logic circuits. newline