Power optimization analysis using power gating technique in deep submicron circuits

Abstract

Power dissipation reduction in Integrated Circuits (IC) is a major challenge during the design of portable systems and high performance processors. In portable systems, the battery life depends on the power dissipation. Also, the increase in leakage current with Very Large Scale Integration (VLSI) technology scaling is a major concern for deep submicron circuit designers. Hence, Complementary Metal Oxide Semiconductor (CMOS) newlinebased design is considered for developing low power ICs. In digital system design, low power consumption may be achieved at device level, process level and algorithm level. This research focuses on minimizing power consumption at circuit level. Efficient circuit level techniques that reduce leakage power dissipation are explored and analysed. Power gating technique is used to reduce leakage power by switching off the supply voltage to idle circuits. To introduce power gating, adoption of multi-threshold CMOS process is required. Simple logic blocks of the design are implemented using low threshold voltage transistors (VTL), whereas the sleep transistors which act as power gate for the design are high threshold voltage transistors (VTH). A conventional 14Transistor full adder is designed using pass transistors and transmission gates. Using the full adder, parallel binary adder is developed and sleep transistors are introduced to reduce the static power consumption. The power gated transistors are switched with high threshold voltage (VTH). 130nm technology is used in the design with 2.5V as the operating voltage. newline newline