Cost effective novel testing approach for vlsi circuits

Abstract

The advent of VLSI technology has given rise to sophistication in the devices which can be incorporated into a single chip. Testing of chips using automated methodologies has taken new dimensions in recent years. Testing the accurate functionality of the chip is an essential step in the production process to improve the yield rates. The chip are vulnerable to failures due to higher clock rates, shrinking geometries, longer wires, increasing metal density and with different types of faults reducing the yield and hence, increases the testing cost. The current processes have reached a point, where many conventional pass/fail testing methods are enhanced by defect based fault models and/or grading-based techniques, assessing the quality of the circuit. An essential step for the whole test process is the generation of test patterns. Test patterns are the primary bit patterns used for testing a digital circuitry. Majority of the logical device developed are tested for all functionality before its practical usage. Design-for test (DFT) techniques aim to reduce the cost of Automatic Test Equipment (ATE) by automatically generating tests through Automatic Test Pattern Generation (ATPG).The generated patterns are used to test semiconductor devices getting manufactured, or to assist with determining the cause of failure. The effectiveness of ATPG is measured by the number of modeled defects, or fault models, detectable and by the number of generated patterns. The type of Circuit Under Test (CUT) can be combinational, full scan, synchronous sequential or asynchronous sequential circuits. The advantage of introducing optimized test pattern directly reduces the testing time. This results in the reduction of testing costs during online testing. An earlier study has shown increase in test pattern generation count between 40-90%.Increase in test patterns faces several problems. Due to presence of limited transfer of data bandwidth between work station and ATE, test patterns require several tens of hours to upload. During this time newline