Architecture and Design of an Integer N Charge Pump Phase Locked Loop for 2 4 GHz Wireless Application

Abstract

Phase Locked Loop is a simple negative feedback architecture that allows economic multiplication of reference frequencies by large variable numbers. It contains the basic blocks such as VCO, Divider, PFD and CP. Conventionally, PFD suffers from dead zone and blind zone, and CP suffers from ripple in the control voltage, which in turn causes reference spurs at the output of VCO. The objective of this research work is to reduce the phase noise, to smoothen the control voltage, and to increase the tuning range of the PLL, by overcoming the design limitations, and by improvising upon the architectural issues. Initially, the general modeling of the Integer-N PLL is performed, by utilizing the 3rd order loop filter. The model is verified for its functionality by considering the reference as 1 MHz and output as 2.4 GHz. D-flip flop based PFD is utilized, along with the current sources for CP. The lock time for the 3rd order Type-II PLL is measured, so as to analyze the loop filter bandwidth. Later on, Ring Oscillator is characterized, whose frequency of operation depends on the delay of each stage. As the 1st order equations design do not hold good in submicron dimensions, it is desirable to have accurate design equations for the Ring Oscillator. In our work, a new formula for the frequency is derived, which does not require the computation of time constant. It is proved that the frequency of oscillations is independent of the width of the devices, and is proportional to the square of the length of the devices. The PFD is designed using TG based latches, in which, the continuous pulses that get produced by the conventional NAND based latches are avoided, leading to reduced power consumption of the PFD. This PFD is found to be dead zone free. With CP, the usage of differential amplifier in between the two limbs is found to reduce the current mismatch. The work is improved by using 2-stage opamp as an error amplifier, and by using TGs in place of switches. Finally the important parameters of the PLL such as, phase noise..