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http://hdl.handle.net/10603/333510
Title: | Analytical modeling and simulation of dual material surrounding gate TFET with stacked gate oxide |
Researcher: | Dharshana, V |
Guide(s): | Balamurugan, N B |
Keywords: | Tunnel Field Effect Transistor Semiconductor industry Low power VLSI |
University: | Anna University |
Completed Date: | 2020 |
Abstract: | For the past three to four decades, manufacturing of integrated circuits in the semiconductor industry have achieved increased growth and improvement to reach high speed and outstanding performance. It has dominated the electronic market with devices for computing, communication, entertainment, automotive and other applications simultaneously with improvements in cost, speed and power consumption. All these merits have been achieved by improving the circuit design and by shrinking of the device dimensions. This idea permits circuits to perform faster and with a lot of functions within the same or smaller area for new technology generation. Fundamentally, the scaling law was introduced by Gordon Moore (1965), states that number of transistors per chip would quadruple every three years or the number of transistor is doubled every 18 months. Scaling takes into account the fabrication of more transistors at a similar cost. The fundamental block present inside the integrated circuit is Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The continuous downscaling applies for MOS device and a silicon/SiO2 material process is almost reaching their physical limits.Hence, Tunnel Field Effect Transistor (TFET) is being considered as one of the most promising devices to replace a conventional MOSFET for low power VLSI applications. However, the major challenge of TFET is its low ION (and#956;A) current. Surrounding gate MOSFET or Gate All Around (GAA) MOSFET is one of the best device and it has the merits of s better scalability, better switching characteristics, higher drive current and higher trans-conductance and linearity. Hence, in this thesis, the concept of surrounding gate structure has been implemented in TFET structure for improving the output characteristics. The aim of this thesis is to develop an analytical surface potential model for HfO2/SiO2 stacked surrounding gate TFET structure has been developed by solving the two dimensional Poisson s equation newline |
Pagination: | xviii,146p. |
URI: | http://hdl.handle.net/10603/333510 |
Appears in Departments: | Faculty of Information and Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
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01_title.pdf | Attached File | 21.87 kB | Adobe PDF | View/Open |
02_certificates.pdf | 189 kB | Adobe PDF | View/Open | |
03_vivaproceedings.pdf | 437.78 kB | Adobe PDF | View/Open | |
04_bonafidecertificate.pdf | 302.38 kB | Adobe PDF | View/Open | |
05_abstracts.pdf | 284.1 kB | Adobe PDF | View/Open | |
06_acknowledgements.pdf | 333.28 kB | Adobe PDF | View/Open | |
07-contents.pdf | 425.6 kB | Adobe PDF | View/Open | |
08_listoftables.pdf | 179.73 kB | Adobe PDF | View/Open | |
09_listoffigures.pdf | 339.9 kB | Adobe PDF | View/Open | |
10_listofabbreviations.pdf | 188.62 kB | Adobe PDF | View/Open | |
11_chapter1.pdf | 1.35 MB | Adobe PDF | View/Open | |
12_chapter2.pdf | 1.04 MB | Adobe PDF | View/Open | |
13-chapter3.pdf | 1.26 MB | Adobe PDF | View/Open | |
14_chapter4.pdf | 863.22 kB | Adobe PDF | View/Open | |
15_chapter5.pdf | 825.71 kB | Adobe PDF | View/Open | |
16_chapter6.pdf | 433.73 kB | Adobe PDF | View/Open | |
17_conclusion.pdf | 284.37 kB | Adobe PDF | View/Open | |
18_references.pdf | 362.55 kB | Adobe PDF | View/Open | |
19_listofpublications.pdf | 280.48 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 91.94 kB | Adobe PDF | View/Open |
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