Design analysis and optimization of cmos low noise amplifier for wireless applications

Abstract

Low Noise Amplifier (LNA) is the first and important block of the receiver side of the communication system. An LNA is required to have low Noise Figure (NF), high Gain, high Third-order Input Intercept Point (IIP3), and low power consumption. In a mobile phone device, multiple receivers are required for communication. Specifically, 5G communication requires a separate receiver for signal reception. A single receiver is used for 2G/3G/4G communications. Bluetooth and Wireless Local Area Network (WLAN) communication receiver requires two numbers of LNAs of 2.4 GHz frequency. In the proposed work, four LNAs are designed for the mobile communication receivers in Cadence virtuoso 90nm technology, which has been selected to meet the frequency requirements of the 5G communication. In the first proposed work, a 2.4 GHz CMOS LNA is designed and optimized for Bluetooth and WLAN applications. Here, the Elephant Herding Optimization (EHO) algorithm is used for the first time to optimize the performance parameters of the LNA. The simulation shows that a maximum gain of 26.7 dB at 2.4 GHz is achieved in the proposed design. Noise cancelation technique is involved to get a reduced noise figure of 1.12 dB. The proposed design consumes 8.9 mW of power from 0.5V and 1.2V supply. Then, current reuse technology is used to reduce the power consumption. The input and output return losses have been found as -18 dB and -15 dB respectively at the targeted 2.4 GHz frequency. The third-order input intercept point (IIP3) of the optimized LNA is -8.1 dBm. The EHO algorithm has improved the performance of the LNA newline