Algorithms for reducing Reconfiguration overheads in Reconfigurable systems

Abstract

Modern embedded systems are packed with dedicated Field- Programmable Gate Arrays (FPGAs) to accelerate the overall system performance. But the main drawback in using FPGA as a reconfigurable system is that a lot of reconfiguration overheads are generated in the reconfiguration process. The reconfiguration overheads are mainly because of the configuration data being fetched from the off-chip memory and also due to the improper management of tasks during execution. To reduce the reconfiguration overheads, an architecture is proposed which consists of High Speed (HS) and Low Energy (LE) memories. In this architecture, the HS emory is optimized for speed and the LE memory is optimized for lesser energy consumption. By efficiently using these on-chip memories, it ispossible to reduce the reconfiguration overheads. The functioning of the multimedia system is divided into static and dynamic. For a static type of system, an architecture with three algorithms is proposed. All the three algorithms use combinations of techniques like task prefetching, reusing and memory mapping. For task prefetching, As Soon As Possible (ASAP) approach is used. Using this approach, it is possible to configure the next task when the current task completes the configuration and enters the execution phase. Memory mapping technique involves in preallocation of tasks among the memory hierarchy (Combination of on-chip and off-chip memories). The main aim of this technique is to place the vital tasks inside the HS memory and non-vital tasks inside the LE memory. Hence during the task graph execution process, less amount of time and energy reconfiguration overheads are produced. newline