Design of a generic architecture for Yavadunam a vedic sutra for Performing squaring and Multiplication operation

Abstract

The growing trend for high speed processing systems, leads to the need for proficient Mathematical operations. In case of high speed applications like Digital signal processing, Image processing, Cryptography, etc. the preferred overall performance is completed by way of better throughput Mathematical operations. Multiplication is the major and commonly used operations in most of the applications. In many excessive speed packages complex multiplications are done by way of squaring operations. A dedicated square hardware may extensively progress the silicon area and reduces the delay to a large extent. newlineIn this work a historical Indian mathematical method is employed to realize squaring and Multiplication operations. Vedic Mathematics resolves mathematical problems in a less demanding way mentally. To work out problems in an easy and fast means Vedic Mathematics affords sets of rules called Sutras or aphorisms and up sutras. These sutras are the word formulae which describes about the actual ways to solve any Mathematical problem. The complexity of calculations in the conventional Mathematics is very much reduced in Vedic Mathematics. Identification of an appropriate sutra for an appropriate application is of much important. In this research work a generic architecture for the squaring sutra of Vedic Mathematics, Yavadunam sutra has been designed. Based on the principles of Yavadunam sutra a novel high speed Vedic Multiplier is constructed. A particular architecture for quick squaring and multiplication operation is designed using Yavadunam and bit reduction technique thereby reducing the components usage with decrease in critical path delay and increasing the speed. Based on the principles of Yavadunam sutra and bit reduction technique a high speed hybrid binary multiplier is designed to improve the speed and reduce the delay. newline newline