Novel radix 16 booth multiplier and wallace multiplier for ultra high power efficiency with reduced complexity

Abstract

The current era in VLSI design, power, delay and area have become the characteristic features of any circuit. The high speed Digital Signal Processor (DSP), FFTs, etc, generally depends on the speed of a multiplier. Multipliers are considered as a more complex component, since it involves more calculation, when compared with adders. The current techniques provide greater access to high-speed multipliers which are designed with less area that consume low power. The major constraints to be considered for an efficient multiplier design are propagationdelay and power dissipation, especially during the ideal time. An approximate recoding adder is proposed to reduce the existing booth multiplierand#8223;s immensity. It reduces the complexity and time delay through this technique; however, it has an issue with Power Delay Product (PDP) and power dissipation. The power dissipation in circuit is an accumulation of dynamic and static power. The power dissipation in the ideal mode is higher and needs more concern to be curtailed. To solve this problem, the proposed system is designed with a power gating based 16x16 bit Radix-16 Booth multiplier implemented with an approximate recoding adder, which minimizes the length and width of the partial products for speeding up the multiplication process. The power gating is implemented in all the circuit elements in this research. Two power gating techniques, Coarse and fine grain, could be adapted in the circuitry to attain the maximum efficiency during the active and idle time operations. The Fine grain methodology is introduced in the circuit for a precise power reduction. It decreases the power dissipation to a greater extent while the device is in the idle condition newline