Enhancing reliability in multi core Systems using low cost fault Tolerant one instruction cores

Abstract

Rapid improvements in the CMOS technology have resulted in an exponential growth of transistor density. Billions of transistors on a chip have led to integration of many cores leading to many challenges such as increased power dissipation, thermal dissipation, occurrence of faults in the circuits and reliability issues. Existing approaches explore the usage of redundancy based solutions for fault tolerance in a multi-core scenario. Redundancy based approaches at core level, thread level, micro-architectural level, and software level improve the reliability of the multi-core systems. Core level techniques improve the lifetime reliability of multi-core systems using low power small cores to provide fault tolerance to larger cores. The multi-core processor architecture with asymmetric cores (large and small cores) has gained momentum and focus from a large number of researchers with respect to fault tolerance. Based on the above implications, design alternatives for modern multi-core system factoring its features are proposed in this thesis. Among the design alternatives, Multi-core system using One Instruction Cores (OIC) is an asymmetric multi-core architecture that has been choosen for reliability modelling in this thesis. OIC is a warm standby - subtract if less Thus, the OIC helps to address the need for a low power small core. When one of the functional units newline