Tsv and slew aware 3d gated clock Tree synthesis

Abstract

Three-Dimensional Integrated Circuit (3D IC) technology offers potential advantages for advanced digital system designs. The technology not only helps to overcome the interconnected wire delay barrier by significantly hortening the wire length from the 2D system, but also provides a solution to minimize power, delay, clock slew and clock skew by stacking multiple logic and connecting them to Through-Silicon-Vias (TSVs). All these features make 3D IC technology a desirable option for TSV and slew aware gated clock tree synthesis. Clock distribution is crucial to a digital system design. While implementing a system in 3D technology, it is more difficult to control the clock skew due to cross-die process variations, high thermal gradients and TSV non-idealities. A major challenge for IC developers is Three Dimensional Integrated Circuits (3D ICs) based on Through Silicon Via (TSV). Previous de-skewing techniques for 2D ICs, such as delay buffer insertion and active de-skewing, introduced significant overheads and require complicated analysis it cannot compensate clock distribution errors caused by TSVs and cross-die variations in 3D ICs. 3D clock network design recently proposed that it has no ability to handle cross-tier variations or oversimplify the effects of TSVs. A new adaptive clock topology is required to implement accurate and balanced clock distribution in 3D ICs. In physical design of Integrated Circuits (ICs) especially after placement, Clock Tree Synthesis (CTS) plays a major part in the general chip efficiency. In this work, new technologies are developed to handle the challenges in 3D CTS. 3D gated CTS on the TSV-TSV coupling model is an effective approach to reduce power, delay and clock skew newline