Low power VLSI design and circuits for digital CMOS technology

Abstract

One of the paramount issues in the field of VLSI design is the rapid increase in power consumption. The need to minimize power consumption became prominent due to the increased demand for high performance portable electronic systems like Personal Digital Assistant, notebook, computer, etc. Every digital system is built with a memory unit in it. Register elements such as latches and flip-flops together with clock network constitute the major power-consuming elements in any design. So the design of power-efficient and high-performance memory elements is necessary. They are in great demand which motivates circuit designers to design low power architecture for both full custom and semi-custom design implementation. A variety of memory element designs have been proposed for different objectives like increased speed, low power, less layout area, etc, but no design has been developed so far which maintains a proper balance between power consumption, area, and speed. Our goal is to design and develop high-performance power- efficient flip-flops and shift registers with the least area and high speed. The performance is boosted up by incorporating different low power reduction techniques in it. Different power reduction techniques are adopted based on its architectural design of each hierarchical level. The major source of power consumption is identified and the design is modified with respect to it. Here, we propose six different power efficient and high-performance designs of memory elements (three flip-flops and three shift registers). The first proposed work focuses on the design of a power-efficient dynamic double edge-triggered flip-flop named TCRFF (Transistor Count Reduction Flip-Flop). It features a dynamic design comprising of transmission gate in which total transistor count has greatly reduced without affecting the logic. The design is such that there is a reduction in high capacitive loading and switching activity of internal nodes along with the usage of dual-edge clocking. newline