Smart patch antenna for DS CDMA system and its implementation on FPGA with adaptive algorithms for mai suppression

Abstract

The principal goal of this research work is focused on designing and then testing the performance of patch antennas coding and decoding circuits implemented on Field Programmable Gate Arrays FPGA for Code Division Multiple Access CDMA Transceiver using extremely simple circuit concepts This research work also describes modulation and demodulation circuit for CDMA The simulated results subsequently have shown quite improved and optimized circuit performance The performance parameter is mainly based on the number of gates used by CDMA sub system and sub circuits on FPGA implementation The functional performance of designed circuits is tested by carrying out simulation using FPGA Very high speed integrated circuits Hardware Description Language VHDL on average fan out of 4 67 for non clock nets on FPGA chip xc6vlx75t 3ff484 and XILINX ISE 12 1 version software and MATLAB 5 platform is explained in chapter 3 newlineFurther research work is concentrated on developing a novel technique or concepts for reducing Multiple Access Interference MAI in Direct Sequence Code Division Multiple Access DS CDMA system prevailing in Wireless Communication The proposed novel algorithm is developed by using the principles of artificial intelligence based on neural newlineNetworks The basic function of the algorithm is to determine interference ratio for more accurately in the presence of variable noise in the channel While considering higher data transfer rate presence of AWGN and channel fading effects due to multipath reflection and diffractions are considered for performance analysis newline newline