Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/330086
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dc.coverage.spatial
dc.date.accessioned2021-07-02T11:54:56Z-
dc.date.available2021-07-02T11:54:56Z-
dc.identifier.urihttp://hdl.handle.net/10603/330086-
dc.description.abstractFile Attached newline
dc.format.extent
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleImplementation of Built In Self Test Using Low Power Test Pattern Generators in Test Per Clock Scheme
dc.title.alternative
dc.creator.researcherJamal.Kovelakuntla
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guideManjunatha Chari.K
dc.publisher.placeVisakhapatnam
dc.publisher.universityGITAM University
dc.publisher.institutionSchool of Technology Hyderabad
dc.date.registered
dc.date.completed2021
dc.date.awarded
dc.format.dimensions
dc.format.accompanyingmaterialNone
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:School of Technology Hyderabad Campus

Files in This Item:
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10_chapter i.pdfAttached File368.52 kBAdobe PDFView/Open
11_chapter-ii.pdf598.83 kBAdobe PDFView/Open
12_chapter-iii.pdf1.05 MBAdobe PDFView/Open
13_chapter-iv.pdf592.18 kBAdobe PDFView/Open
14_chapter v.pdf893.3 kBAdobe PDFView/Open
15_chapter vi.pdf440.6 kBAdobe PDFView/Open
16_references.pdf492.52 kBAdobe PDFView/Open
17_list of publications.pdf345.71 kBAdobe PDFView/Open
1_title.pdf301.16 kBAdobe PDFView/Open
2_certificate.pdf209.15 kBAdobe PDFView/Open
3_abstract.pdf361.52 kBAdobe PDFView/Open
4_declaration.pdf184.79 kBAdobe PDFView/Open
5_acknowledgement.pdf187.81 kBAdobe PDFView/Open
6_table of contents.pdf383.51 kBAdobe PDFView/Open
7_list of tables.pdf359.18 kBAdobe PDFView/Open
80_recommendation.pdf368.52 kBAdobe PDFView/Open
8_list of figures.pdf350.26 kBAdobe PDFView/Open
9_abbreviations.pdf350.46 kBAdobe PDFView/Open


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