Low jitter phase locked loop architectures for high speed clock generation

Abstract

High performance digital systems widely use Phase Locked Loops newlinePLLs for generating well timed onchip clocks As the operating frequency newlineincreases the performance of these systems is significantly affected by a newlinetiming jitter or phase noise The jitter directly reduces the performance of the newlinesequential circuit Keeping it within strict bounds is essential to ensure the newlineperformance Also for applications such as high speed parallel links and newlinedistributed synchronous clocking multiple PLLs are employed to minimize newlinethe timing uncertainty Therefore the demand for lowjitter PLLs has been newlineincreasing The low jitter clock requirement makes the design of low jitter newlinePLL even more challenging newline newline