1. Shodhganga@INFLIBNET
  2. Pacific University
  3. computer science
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/321727
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DC FieldValueLanguage
dc.coverage.spatial
dc.date.accessioned2021-04-22T06:51:55Z-
dc.date.available2021-04-22T06:51:55Z-
dc.identifier.urihttp://hdl.handle.net/10603/321727-
dc.description.abstractnewline
dc.format.extent
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleDesign and Modelling of All Digital Phase Locked Loop Using VLSI
dc.title.alternative
dc.creator.researcherAnupama P. Patil
dc.subject.keywordComputer Science
dc.subject.keywordComputer Science Artificial Intelligence
dc.subject.keywordEngineering and Technology
dc.description.note
dc.contributor.guideP.H. Tandel
dc.publisher.placeDebari
dc.publisher.universityPacific University
dc.publisher.institutioncomputer science
dc.date.registered
dc.date.completed2019
dc.date.awarded
dc.format.dimensions
dc.format.accompanyingmaterialCD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:computer science

Files in This Item:
File Description SizeFormat 
01_cover page - anupama patil.pdfAttached File67.99 kBAdobe PDFView/Open
02_certificate by supervisor.pdf - anupama patil.pdf67.24 kBAdobe PDFView/Open
03_acknowledgment and abstract - anupama patil.pdf58.53 kBAdobe PDFView/Open
80_recommendation.pdf53.71 kBAdobe PDFView/Open
addpll thesis chapter 1 final - anupama patil.pdf132.05 kBAdobe PDFView/Open
addpll thesis chapter 2 final - anupama patil.pdf186.05 kBAdobe PDFView/Open
addpll thesis chapter 3 final - anupama patil.pdf1.45 MBAdobe PDFView/Open
addpll thesis chapter 4 final - anupama patil.pdf532.45 kBAdobe PDFView/Open
chapter 5finaladpll - anupama patil.pdf1.31 MBAdobe PDFView/Open
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